专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1nsmodule calculation(input clk,input rst_n,input [3:0] a,input [3:0] b,output [8:0] c);reg [8:0] data1, data2 ; assign c = data2 ; always @ (posedge clk or negedge rst_n) begin if (!rst_n) data1 <= 0 ; else data1 <= (a << 3) + (a << 2) + (b << 2) + (b << 0) ; endalways @ (posedge clk or negedge rst_n) begin if (!rst_n) begindata1 <= 0 ; data2 <= 0 ; endelse data2 <= data1 ; endendmodule