verilog 仿真器显示ascII码。

module ascii_display;

reg [7:0] ascii_code;

initial begin
ascii_code = 8'h00; // 初始值为0
repeat (128) begin
$display("ASCII Code: %h, Character: %c", ascii_code, ascii_code);
#1 ascii_code = ascii_code + 8'h01; // 逐个递增ASCII码
end
end

initial begin
$dumpfile("ascii_display.vcd");
//$dumpvars; //无参数，表示设计中的所有信号都将被记录
$dumpvars(0,ascii_display);
end
endmodule