pll锁相环
总线
gating
rk3568.dtsi
pmucru: clock-controller@fdd00000 {compatible = "rockchip,rk3568-pmucru";reg = <0x0 0xfdd00000 0x0 0x1000>;rockchip,grf = <&grf>;rockchip,pmugrf = <&pmugrf>;#clock-cells = <1>;#reset-cells = <1>;assigned-clocks = <&pmucru SCLK_32K_IOE>;assigned-clock-parents = <&pmucru CLK_RTC_32K>;
};cru: clock-controller@fdd20000 {compatible = "rockchip,rk3568-cru";re
