专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1nsmodule sale(input                clk   ,input                rst_n ,input                sel   ,//sel=0,5$dranks,sel=1,10&=$drinksinput          [1:0] din   ,//din=1,input 5$,din=2,input 10$output   reg  [1:0] drinks_out,//drinks_out=1,output 5$ drinks,drinks_out=2,output 10$ drinksoutput	reg        change_out   
);reg [1:0] state, nstate ; parameter idle = 0, x = 1 ; // idle : 空闲i.e.无钱； x state : 饮料机输出饮料B但只投了5块钱；always @ (posedge clk or negedge rst_n) if (!rst_n) state <= idle ; else state <= nstate ; always @ (*) case (state) idle : nstate = sel ? (din == 1 ? x : idle) : idle ; x : nstate = din == 0 ? x : idle ; default : nstate <= idle ; endcasealways @ (posedge clk or negedge rst_n) if (!rst_n) drinks_out <= 0 ; else if (!sel) if ((state == idle && din == 1) || (state == idle && din == 2)) drinks_out <= 1 ; else drinks_out <= 0 ; else if ((state == idle && din == 2) || (state == x && din == 1) || (state == x && din == 2)) drinks_out <= 2 ; else drinks_out <= 0 ;always @ (posedge clk or negedge rst_n) if (!rst_n) change_out <= 0 ; else if ((sel == 0 && state == idle && din == 2) || (sel && state == x && din == 2)) change_out <= 1 ; else change_out <= 0 ; endmodule