题目描述

  分别编写一个数据发送模块和一个数据接收模块，模块的时钟信号分别为clk_a，clk_b。两个时钟的频率不相同。数据发送模块循环发送0-7，在每个数据传输完成之后，间隔5个时钟，发送下一个数据。请在两个模块之间添加必要的握手信号，保证数据传输不丢失。
  模块的接口信号图如下：

data_req和data_ack的作用说明：
  data_req表示数据请求接受信号。当data_out发出时，该信号拉高，在确认数据被成功接收之前，保持为高，期间data应该保持不变，等待接收端接收数据。
  当数据接收端检测到data_req为高，表示该时刻的信号data有效，保存数据，并拉高data_ack。
  当数据发送端检测到data_ack，表示上一个发送的数据已经被接收。撤销data_req，然后可以改变数据data。等到下次发送时，再一次拉高data_req。

输入描述：
   clk_a：发送端时钟信号
   clk_b：接收端时钟信号
   rst_n：复位信号，低电平有效
   data_ack：数据接收确认信号

输出描述：
   data：发送的数据
   data_req：请求接收数据

自解

`timescale 1ns/1ns
// 20240301
module data_driver(input   clk_a,input   rst_n,input           data_ack,output reg [3:0]data    ,output reg      data_req);initial begindata     = 4'b0;data_req = 1'b0;end/*********  CDC processing start  ***********/reg data_ack_d1_r, data_ack_d2_r;always @(posedge clk_a) begindata_ack_d1_r <= data_ack;data_ack_d2_r <= data_ack_d1_r;end/*********  CDC processing end  *************/reg [1:0] cs = 2'h0, ns;reg [3:0] data_r = 4'd0;reg [2:0]   timeout_cnt_r   = 3'd0;reg         timeout_flag_r  = 1'b0;always @(posedge clk_a, negedge rst_n) beginif (~rst_n) begincs <= 2'h0;end else begincs <= ns;endendalways @(*) begincase (cs)2'h0: beginns = 2'h2;end2'h1: beginif (data_req & data_ack_d2_r) beginns = 2'h2;end else beginns = 2'h1;endend2'h2: beginif (timeout_flag_r) beginns = 2'h1;end else beginns = 2'h2;endenddefault: beginns = 2'h0;endendcaseendalways @(posedge clk_a) begincase (ns)default: begindata_req    <= 1'b0;data        <= 4'd0;data_r      <= 4'd0;end2'h1: begindata_req    <= 1'b1;data        <= data_r;if (data_req & data_ack_d2_r) begindata_r  <= data_r + 4'd1;endend2'h2: begindata_req    <= 1'b0;data        <= data;data_r      <= data_r;endendcase        endalways @(posedge clk_a) begincase (ns)default: begintimeout_cnt_r   <= 3'd0;timeout_flag_r  <= 1'b0;end2'h2: begintimeout_cnt_r   <= timeout_cnt_r + 3'd1;if (timeout_cnt_r == 3'd4) begintimeout_flag_r <= 1'b1;end else begintimeout_flag_r <= 1'b0;endendendcaseendendmodulemodule data_receiver(input clk_b,input rst_n,output reg data_ack,input [3:0] data,input data_req);initial begindata_ack = 1'b0;end/***********  CDC processing start  ************/reg [3:0]   data_d1_r, data_d2_r;reg         data_req_d1_r, data_req_d2_r;always @(posedge clk_b) begindata_d1_r <= data;data_d2_r <= data_d2_r;data_req_d1_r <= data_req;data_req_d2_r <= data_req_d1_r;end/***********  CDC processing end  *************/reg [1:0] cs = 2'h0, ns;always @(posedge clk_b, negedge rst_n) beginif (~rst_n) begincs <= 2'h0;end else begincs <= ns;endendalways @(*) begincase (cs)2'h0: beginns = 2'h1;end2'h1: beginns = 2'h1;enddefault: beginns = 2'h0;endendcaseendalways @(posedge clk_b) begincase (ns)default: begindata_ack <= 1'b0;end2'h1: begindata_ack <= 1'b1;endendcaseendalways @(posedge clk_b) begincase (ns)2'h1: beginif (data_ack & data_req_d2_r) begin// data_d2_r validateendendendcaseendendmodule